Flexibility is key to FPGA success, but speed is equally important. Achronix almost triples the throughput of the system by taking clock gating to the extreme. The Achronix Speedster FPGAs use a ...

One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.

When combined with advances in FPGA technologies that ease complex interface design efforts, Chronology's TimingDesigner can simplify design issues and provide advanced accurate control of high-speed ...

No discussion on FPGA design is complete without addressing the issues associated with transferring signals that are not synchronized to the clock into clocked logic. While this should be a digital ...

Clock domain crossings are significant sources of field system failures. Despite this fact, designs continue to be released without fully verified CDCs. A false sense of security resulting from ...

It used to be that designing hardware required schematics and designing software required code. Sure, a lot of people could jump back and forth, but it was clearly a different discipline. Today, a lot ...

Over a few short years, FPGA technology has advanced significantly. These devices have become extremely complex. FPGA blocks continue to maintain the phase-locked loop (PLL) technology capable of ...

With the advent of new technologies in IC design and complexity of the business models, chip designers may want to explore different choices available to them for implementation. ASICs have been the ...

[John] wanted a project to help him learn more about FPGAs. So he started with his wooden clock — made with an Arduino — and ported it over to a Lattice FPGA using Icestorm. What’s nice is that he ...

Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC issues on design functionality grows ...