Electronic Design

Equivalence Checker Formally Verifies Bug-Free RTL Clock Gating

Clock-gating techniques for power management are coming into greater favor among RTL designers. Often, designers will instantiate clock gating as a means of conserving power by turning off the clocks ...
EDN

Xilinx ISE Design Suite 12 Enables Up to 30% Dynamic Power Reduction with Intelligent Clock-Gating Technology

SAN JOSE, Calif., May 3 /PRNewswire/ — Xilinx (Nasdaq: XLNX) today introduced the ISE® Design Suite 12 software to enable breakthrough optimizations for power and cost with greater design productivity ...
Electronic Design

1.5-GHz FPGA Takes Clock Gating To The Max

Flexibility is key to FPGA success, but speed is equally important. Achronix almost triples the throughput of the system by taking clock gating to the extreme. The Achronix Speedster FPGAs use a ...
EDN

Recursive clock gating: Performance implications

With so much buzz around low power wearable electronics, designers are looking to save every last nanowatt of power in their design. Clock gating, which arguably is the most efficient and most simple ...