Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.

As semiconductor technology pushes the boundaries of scale and complexity, traditional VLSI physical design methodologies are struggling to keep pace. The rise of Artificial Intelligence (AI), ...

Editor's Note: In Part 3 of this series, consultant and ASIC designer Tom Moxon covered several RTL and logic synthesis design flows. In this installment of the series, he'll describe new physical ...

In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, ...

Design software is transforming the design process at a swift pace. Some of the advances are due to new technology such as Artificial Intelligence (AI). Other advances are due to the demands of user ...

Cadence Design Systems has started bringing artificial intelligence (AI) into the fold on its flagship chip design suite to help designers build smaller, faster processors that consume less power and ...

Like other EDA vendors, Siemens EDA has over the past few years been adding artificial intelligence and machine learning capabilities to its suite of EDA (electronic design automation) tools. At the ...

Physical AI holds the promise of making everything from robots to a slew of mobile edge devices much more interactive and useful, but it will significantly alter how systems are designed, verified, ...