Scan insertion to improve test coverage and reduce test pattern volume is very common in today’s DFT tools. All of the major ATPG tool vendors (Synopsys, Cadence, and Mentor) offer this approach in ...

In 2001, Mentor Graphics introduced a compression technology called Embedded Deterministic Test (EDT).3 EDT uses very simple logic added to the scan chain inputs and outputs to enable compression ...

IC designers now have a powerful weapon in the struggle against rising test costs: commercially available EDA solutions that provide fast and effective means to implement scan compression on-chip. By ...