SOLVED: Cadence: Draw schematic for NAND-2 gate. Build testbench schematic, including sources to test all four input conditions of the gate, using transient simulation. 1. You should have separate voltage sources for the two inputs, in addition to the supply voltage. 2. One approach is to use "vpulse" type sources with varying periods, so that together they traverse all input combinations. 3. Measure the rising-output propagation delay from each input: tPpLHA and tppLHB.
SOLVED: Cadence: Draw schematic for NAND-2 gate. Build testbench …
May 1, 2023
numerade.com
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